Job Summary
We are looking for skilled Memory Layout Engineers with hands-on experience in custom layout design, physical verification, and layout optimization for memory circuits. The ideal candidate should have a strong understanding of CMOS technology, layout design principles, and memory circuit architectures.
Key Responsibilities
• Design and develop custom layouts for memory circuits such as SRAM, ROM, and other memory macros.
• Work on memory bitcells, row decoders, column decoders, sense amplifiers, write drivers, and peripheral circuits.
• Perform physical verification, including DRC, LVS, and ERC.
• Ensure layout quality, matching, symmetry, and adherence to design rules.
• Optimize layout for area, power, performance, and signal integrity.
• Analyze and resolve layout-related issues, including parasitic effects and connectivity violations.
• Collaborate with circuit design, physical design, and verification teams to meet project requirements.
• Support layout reviews, debugging, and design sign-off activities.





Required Skills
• 3+ years of relevant experience in Memory Layout or Custom Layout Design.
• Solid hands-on experience in SRAM layout and memory-related circuits.
• Good knowledge of CMOS technology and analog layout fundamentals.
• Experience with Cadence Virtuoso Layout Editor.
• Proficiency in physical verification tools and debugging DRC/LVS violations.
• Understanding of matching techniques, latch-up prevention, guard rings, shielding, and parasitic reduction.
• Familiarity with advanced technology nodes and design-rule requirements is an added advantage.

Preferred Qualifications
• Bachelor's or Master's degree in Electronics, Electrical Engineering, or VLSI-related fields.
• Experience working on advanced-node memory layouts.
• Knowledge of memory bitcell architecture and layout optimization techniques.

📌 Senior Memory Layout Engineer (India)
🏢 Leadsoc Technologies
📍 India