Detailed Skill Set: - Bitcell Design - Design of simpler memory blocks (decoding, rowdec, SA, IO block w/o RA, WA) - Design of complex blocks like RA, WA, Rd selftime and write selftime - SPRAM/Dual Port/ROM architecture - Sense Amp Analysis(offset, pulse width, glitch, coupling etc.)" - Read/Write Selftime Analysis - Functional/Power Marginality analysis - Latch analysis - ESPCV - Power ON and power sequencing checks - Extraction, IR/EM analysis, PERC etc. - Nice to have - Timing, power, leak etc. setups(definitions, stimuli, MCF etc.) - Timing, power, leak etc. verification (current addition) - LVF analysis and implementation - Critical Path Tight Stimuli (CPTS) - Full Cut Tight Stimuli (FCTS) - FC power, timing, power, leak and comparison with CP - Decoupling CAP Ageing (char)

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📌 Associate III - VLSI MCD ST (Noida)
🏢 UST
📍 Noida