Responsibilities
- SRAM bitcell layout
- memory peripherals layout (Row/Column Decoders, Sense Amplifiers, Pre-charge, Write Drivers, Read/Write Assist, IO and Self-Timing)
- Single-Port SRAM, Dual-Port SRAM and ROM architectures
- full memory macro floorplanning and block integration
- critical signal routing
- parasitic-aware layout techniques
- DRC, LVS, ERC and parasitic extraction
- power grid design, decoupling capacitance and power sequencing
- post-layout extracted simulations and optimization
- Experience with industry-standard custom layout and physical verification tools
- Exposure to advanced technology nodes and SRAM compiler development is preferred
- Experience
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📌 Technical Lead I - VLSI ML ST (Noida)
🏢 UST
📍 Noida