- Strong expertise in USB 2.0/3.0 or Ethernet protocols.
- Knowledge of AHB, AXI, MACsec, and PTP protocols is a plus.
- Proficiency in Verilog and SystemVerilog (mandatory).
- Hands-on experience with at least one verification methodology: OVM or UVM (mandatory).
- Experience with at least one EDA simulation tool: QuestaSim, VCS, NCSim, or NCVerilog (mandatory).
- Proven experience in developing testbench components at both block-level and SoC-level verification environments.
- Experience in creating test plans and developing test sequences.
- Understanding of functional coverage, code coverage, and assertion-based verification.
- Solid debugging and problem-solving skills related to RTL, testbench environments, and test failures.
Added Advantage
- Experience with industry-standard Ethernet protocols, specifically 100BASE-T1 and 1000BASE-T1 (IEEE 802.3 Clauses 96 and 97).
- Experience with USB2.0, USB3 GEN1/GEN2 HUB controller verification.