Technical Architect – Design for Test (DFT)

Location: Bengaluru

Experience: 12–16 Years

Role Overview

We are seeking a highly experienced Technical Architect – DFT to define and drive DFT architecture, methodology, and implementation for complex ASIC/SoC designs. The role requires deep technical expertise in MBIST, ATPG, scan insertion, and end-to-end DFT sign-off, with ownership of test architecture, coverage optimization, and design-for-manufacturing requirements.

Key Responsibilities

- Define and drive DFT architecture and test strategies for complex IP and SoC designs.
- Own scan architecture, scan insertion, scan compression, and DFT RTL integration.
- Architect and implement MBIST solutions, including memory test algorithms, controller integration, and verification.
- Drive ATPG pattern generation, fault simulation, pattern validation, and test coverage closure.
- Develop DFT specifications, implementation plans, and sign-off methodologies.
- Optimize stuck-at, transition-delay, and other relevant fault coverage while managing test time and pattern volume.
- Drive DFT rule checking, testability analysis, and resolution of DFT violations.
- Collaborate with RTL, Physical Design, Verification, and Silicon Validation teams to ensure seamless DFT integration.
- Debug DFT-related issues and support silicon bring-up, manufacturing test, and yield improvement.
- Evaluate DFT flows, establish reusable methodologies,



and provide technical guidance to engineering teams.

Required Technical Skills

- 12–16 years of hands-on experience in DFT architecture and implementation for ASIC/SoC designs.
- Robust expertise in DFT architecture, scan insertion, and ATPG.
- In-depth experience with MBIST architecture, integration, and verification.
- Strong understanding of scan compression, scan-chain architecture, and test-point insertion.
- Hands-on experience with ATPG pattern generation, fault modeling, fault simulation, and coverage analysis.
- Expertise in DFT rule checking, testability analysis, and DFT sign-off.
- Experience with industry-standard DFT tools such as Synopsys TestMAX, Siemens Tessent, or equivalent.
- Strong understanding of stuck-at and transition-delay fault models, test coverage, and manufacturing test requirements.
- Knowledge of DFT timing, area, power, and physical implementation trade-offs.

Preferred Qualifications

- Experience with LBIST, JTAG/IEEE 1149.1, boundary scan, and hierarchical DFT.
- Exposure to advanced technology nodes and complex SoC test architectures.
- Experience with post-silicon DFT debug, ATE integration, and silicon yield analysis.
- Strong technical leadership, architecture documentation, and cross-functional problem-solving skills.

Education B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, or a related discipline.

📌 Technical Architect – Design for Test (DFT) (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru