Company Description F.

Robin

Technologies, a division of F.

Robin

Group, is the technology flagship of a diversified industrial conglomerate, delivering integrated solutions across PCB design, electronics manufacturing, and workforce deployment. Supported by over 2,500 professionals and group companies in energy, industrial packaging, and infrastructure, the organization is equipped to handle complex, large-scale engineering projects and long-term engagements. Its core technical pillars include high-density PCB layout, multi-layer board design, semiconductor R&D; support, and Design for Manufacturing to optimize performance, manufacturability, and cost. The company also provides end-to-end electronics manufacturing services from prototyping to volume production, backed by strong quality control and supply chain management. Headquartered at KOSMO ONE in Chennai, F.

Robin

Technologies engages with global clients seeking robust engineering and strategic workforce solutions.

Role Description The Senior DV PCIe Verification Engineer will be responsible for leading and executing verification activities for PCIe-based IP and SoC subsystems, ensuring functional correctness, performance, and compliance with relevant specifications. Day-to-day tasks include building and maintaining verification environments, developing test plans, writing and reviewing test cases, creating and analyzing coverage metrics, and driving closure on verification milestones. The role involves close collaboration with RTL design, architecture, and validation teams to debug complex issues, implement verification methodologies, and improve overall product quality and reliability.

This is a contract, on-site role based in Bengaluru, requiring regular interaction with cross-functional engineering teams and adherence to project timelines and verification best practices.

Qualifications

Experience: 8+ Years

Location: Bengaluru

Education: B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, Computer Engineering, or related field

Role Summary





We are seeking an experienced PCIe Verification Engineer with 8+ years of expertise in IP, Subsystem, and SoC-level verification. The candidate should have strong hands-on experience in PCIe protocol verification, System Verilog, UVM, coverage closure, assertions, and verification methodology development. The role involves developing scalable verification environments, debugging complex issues, and driving verification signoff for PCIe-based designs.

Key Responsibilities

- Develop and execute comprehensive verification plans for PCIe IP/Sub-system/SoC.
- Design and maintain reusable UVM-based verification environments.
- Create directed and constrained-random test cases.
- Develop scoreboards, monitors, checkers, assertions, and functional coverage models.
- Perform protocol compliance verification for PCIe Gen3/Gen4/Gen5/Gen6.
- Execute regression testing, debug failures, and perform root-cause analysis.
- Drive code coverage and functional coverage closure.
- Collaborate closely with RTL designers, architecture teams, and validation teams.
- Participate in specification reviews and verification signoff activities.
- Mentor junior engineers and review verification deliverables.

Required Skills:

Verification Expertise

- Strong experience in SystemVerilog and UVM
- Expertise in:
- Test Planning
- Verification Planning
- Coverage Planning & Closure
- Assertions (SVA)
- Constrained Random Verification
- Scoreboards, Checkers, Monitors
- Regression Management & Debug

Protocol Expertise

- Solid experience in:
- PCIe Gen3/Gen4/Gen5/Gen6
- PCIe LTSSM
- Transaction Layer
- Data Link Layer
- Physical Layer
- Good understanding of:
- AXI/AHB/APB
- CXL (Preferred)
- DDR/UCIe (Nice to have)

Tools

- Synopsys VCS
- Cadence Xcelium
- Mentor Questa
- Verdi Debugger
- Coverage and Regression Tools

Programming & Scripting

- Python
- Perl/Shell/TCL scripting

Preferred Qualifications

- Experience with PCIe Compliance and Interoperability Testing.
- Experience in SoC verification and subsystem integration.
- Exposure to Formal Verification and Emulation Platforms.
- Experience with GLS (Gate Level Simulation).
- Knowledge of CXL protocols is an added advantage

📌 Senior DV PCIe Verification Engineer (Bengaluru)
🏢 F. Robin Technologies | A Division of F. Robin Group
📍 Bengaluru