Job highlights

- Prior experience with on-chip memory subsystem and scheduling / arbitration design
- Experience with Ethernet and IP protocols . Bachelors of Engineering .
- Masters of Engineering
- Minimum Qualifications
- Preferred Qualifications
- 8+ years of experience in RTL engineering related roles . Hands-on knowledge of SystemVerilog and Verilog .

Position Overview We are seeking experienced RTL designers to help define and implement our industry-leading Networking ASICs. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking chips.

Responsibilities

- Packet buffering, queuing, and scheduling: Work on micro architecture and design implementation of high-speed networking ASICs, focusing on latency optimization and quality of service (QoS) support. Prior experience with on-chip memory subsystem and scheduling/arbitration design.
- Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Work with verification team to conduct thorough testing and validation to ensure functionality and reliability.
- Performance Optimization: Analyze and optimize pipelining architectures to improve performance metrics.
- Protocol Support:



Provide support for various networking protocols such as Ethernet and IP protocols, and high speed interconnects such as UCIe.
- Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing, working closely with cross-functional teams, including system architects, hardware engineers, and firmware developers.

Minimum Qualifications

- 8+ years of experience in RTL engineering related roles
- Hands-on knowledge of SystemVerilog and Verilog
- Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments
- Proven expertise in designing and optimizing scheduling and QoS mechanisms
- Experience with Ethernet and IP protocols

- Bachelors of Engineering

Preferred Qualifications

- 8+ years of experience
- Robust analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues.
- Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.

- Masters of Engineering

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 RTL Engineer (Bengaluru)
🏢 Eridu AI
📍 Bengaluru