Here is a comprehensive and standard (JD) template for a Lead Physical Design Engineer. You can easily copy, paste, and adjust the bracketed information to fit your specific company or team needs.

Job Title: Lead Physical Design Engineer

Location: [City, State / Remote / Hybrid] Department: [Hardware / Silicon Engineering] Reports To: [Director of Physical Design / Engineering Manager]

Role Overview

We are seeking an experienced and highly driven Lead Physical Design Engineer to drive the physical implementation of our next-generation, high-performance SoCs. In this role, you will lead a team of engineers through the entire RTL-to-GDSII lifecycle. You will take ownership of complex block-level and top-level physical design tasks, ensure aggressive timing and power closure, and deliver high-quality tape-outs on advanced technology nodes.

Key Responsibilities

- Technical Leadership: Guide, mentor, and manage a team of physical design engineers. Define execution strategies, allocate block-level resources, and track progress against tape-out schedules.

- End-to-End Implementation: Drive core physical design activities, including complex Floor planning, Power Grid design, Placement, Clock Tree Synthesis (CTS), and Routing.

- Synthesis & Timing Closure: Manage physical synthesis and drive Static Timing Analysis (STA) for rapid timing closure (setup, hold, SI/crosstalk) across multi-mode, multi-corner (MMMC) scenarios.

- Power & Reliability: Execute power intent (UPF/CPF), perform comprehensive EM/IR-drop analysis, and resolve dynamic and static voltage drop issues.

- Physical Verification (Sign-off): Ensure tape-out readiness by achieving clean DRC, LVS, Antenna,



and ERC checks.

- Cross-Functional Collaboration: Partner closely with RTL, DFT, Custom Layout, and Architecture teams to iterate on floorplans, resolve congestion, and optimize Power, Performance, and Area (PPA) metrics.

- Flow & Methodology: Develop, maintain, and optimize automation scripts and design flows to eliminate bottlenecks and improve team productivity.

Requirements

- Education: Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.

- Experience: 7–10+ years of hands-on experience in Physical Design, with at least 2+ years acting as a technical lead or manager.

- Technology Nodes: Proven track record of successful tape-outs in advanced FinFET/GAA technology nodes (e.g., 7nm, 5nm, 3nm).

- EDA Tool Expertise: Deep proficiency in industry-standard tools:
- Place & Route: Synopsys ICC2 / Fusion Compiler OR Cadence Innovus.

- Sign-off Timing: Synopsys PrimeTime OR Cadence Tempus.

- Physical Verification: Siemens Calibre, Synopsys ICV, OR Cadence Pegasus.

- Power Analysis: RedHawk OR Voltus.

- Scripting & Automation: Robust programming/scripting skills in TCL, Python, Perl, and Make.

- Soft Skills: Excellent problem-solving, debugging, and communication skills with the ability to articulate complex technical issues to cross-functional stakeholders.

Preferred Qualifications

- Experience with high-frequency CPU/GPU core implementations.

- Familiarity with advanced packaging methodologies (e.g., 2.5D, 3D-IC, Chiplets).

- Knowledge of machine learning (ML) optimization features within modern EDA tool suites.

📌 Lead Physical Design Engineer (Bengaluru)
🏢 SignOff Semiconductors
📍 Bengaluru