Front-End Lead Engineer SoC Integration (RTL / ASIC / VLSI)

1. Position Details

- Client: Broadcom
- Location: Electronic City, Bangalore
- Work Mode: Work from Office (5 Days/Week)
- Experience: 8 12 Year
- Open Positions: 1
- Role Type: Individual Contributor (IC)
- Domain: Semiconductor | ASIC Design | SoC Integration | Front-End VLSI

1. Role Overview

We are seeking an experienced Front-End Lead Engineer specializing in SoC Integration and ASIC Front-End Design. The role involves chip-level integration of proprietary IP blocks, RTL integration, clock and reset architecture, timing constraints, synthesis, and design signoff activities.

The candidate will work closely with the Chip Integration Lead to ensure integration quality, timing closure readiness, and compliance with SoC design methodologies.

Strong hands-on experience in large-scale SoC integration, industry-standard interfaces, Static Timing Analysis (STA), and synthesis is essential. 5. Technical Skills

Specific EDA tool exposure is desirable; equivalent tool experience is acceptable unless otherwise specified by the hiring team.

- Key Responsibilities
- Perform chip-level and SoC-level integration of proprietary IP blocks and subsystems into complex ASIC/SoC designs.
- Own RTL integration activities, including module connectivity, interface compatibility, and integration-level design checks.
- Integrate and validate industry-standard interfaces such as Ethernet, PCIe, AXI, and SPI.
- Collaborate with the Chip Integration Lead on SoC architecture, integration methodology, and implementation requirements.




- Develop and implement clocking and reset methodologies across multiple clock and reset domains.
- Define, review, and maintain timing constraints using Synopsys Design Constraints (SDC) and Static Timing Analysis (STA).
- Execute and analyze RTL Lint and Clock Domain Crossing (CDC) checks to identify and resolve design issues.
- Perform RTL synthesis and analyze area, timing, and power optimization opportunities.
- Support optimal memory selection and integration, considering performance, area, and power requirements.
- Debug RTL integration issues, protocol connectivity problems, timing violations, and synthesis-related errors.
- Coordinate with design, verification, physical design, and timing teams to resolve integration and signoff issues.
- Maintain integration documentation, design checklists, constraint files, and signoff reports.

- Required Qualifications
- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline.
- 8 12 years of relevant semiconductor industry experience.
- Robust hands-on experience in ASIC/SoC Front-End Design and chip-level RTL integration.
- Proven experience integrating multiple IP blocks into large, complex SoCs.
- Practical understanding of Ethernet,



PCIe, AXI, and SPI interfaces.
- Experience with clock and reset methodologies, STA, RTL synthesis, Lint, and CDC.
- Understanding of synthesis constraints, timing optimization, and memory integration.
- Experience working with cross-functional ASIC design and implementation teams.
- Ability to independently manage assigned SoC integration deliverables.
- SoC Integration & RTL Design
- SoC Integration / Chip-Level Integration
- ASIC Front-End Design

- RTL Design and Integration

- Verilog / SystemVerilog
- IP Integration and Subsystem Connectivity
- Large-Scale SoC Architecture

- Interface Protocols

- Ethernet

- PCI Express (PCIe)

- AMBA AXI

- SPI
- Protocol Integration and Interface Connectivity
- Clocking, Reset & Timing
- Clock Architecture and Clock Domain Management
- Reset Architecture and Reset Domain Management

- Static Timing Analysis (STA)

- Timing Constraints / SDC

- Timing Violation Analysis

- Clock Domain Crossing (CDC)
- Synthesis & Signoff

- RTL Synthesis

- Logic Synthesis

- Lint Checks and Signoff

- CDC Analysis and Signoff

- Timing and Area Optimization
- Power, Performance and Area (PPA) Awareness

- Memory Integration
- SRAM / Memory Macro Integration

- Memory Selection and Configuration
- Memory Area, Power and Performance Trade-offs

- EDA Tools Relevant Experience
- Synopsys Design Compiler / Fusion Compiler

- Synopsys PrimeTime
- Synopsys SpyGlass Lint / CDC

- Cadence Genus
- Equivalent industry-standard EDA tools

📌 Front-End Lead Engineer – SoC Integration (RTL / ASIC / VLSI) (Bengaluru)
🏢 Best NanoTech
📍 Bengaluru