The Full Chip STA Engineer will be responsible for performing end-to-end Static Timing Analysis for complex ASIC and SoC designs, ensuring timing closure across multiple modes and corners.

Responsibilities

- Perform full-chip timing analysis from early investigation through final implementation and tape-out.

- Perform static timing analysis and timing closure across multiple functional and test modes and corners.

- Develop, validate, and maintain timing constraints (SDC) for block and full-chip designs.

- Analyze timing scenarios and define appropriate margin strategies in collaboration with Synthesis and Design teams.

- Partner with Physical Design teams to debug timing violations and close designs through PnR and ECO cycles.

- Support timing signoff using industry-standard STA tools such as PrimeTime, Tempus, or equivalent.

- Analyze setup/hold violations, clock paths, crosstalk, OCV/AOCV/POCV, and signal integrity issues.

- Work closely with RTL, Physical Design, DFT, Synthesis, and other cross-functional teams to achieve timing closure.

- Support development and implementation of timing methodologies and signoff flows.

- Prepare timing reports, signoff documentation, and summaries to support project milestones and tape-out.

Requirements

- 3-5 years of relevant experience in Static Timing Analysis (STA).

- Full-chip STA experience is mandatory.





- Prior experience working on AMD projects/products is highly preferred.

- Strong hands-on experience in ASIC timing constraints development, validation, and timing closure.

- Proficiency with industry-standard STA tools such as PrimeTime, Tempus, or equivalent.

- Solid understanding of SDC, MCMM analysis, setup/hold checks, timing signoff methodologies, and ECO-driven timing closure.

- Experience driving timing closure across both functional and test modes.

- Good knowledge of deep sub-micron timing challenges, including crosstalk, noise/glitch analysis, OCV/AOCV/POCV, variation-aware timing, and signal integrity.

- Working understanding of Physical Design flows, including placement, CTS, routing, PnR, and ECO implementation.

- Proficiency in scripting languages such as TCL, Perl, Python, Shell/C-Shell, or Bash for automation and flow development.

- Exposure to advanced technology nodes (7nm, 5nm, or below) is a plus.

- Robust analytical, debugging, and problem-solving skills with effective written and verbal communication.

- Demonstrated ability to collaborate with cross-functional teams and deliver results in a fast-paced project environment.

- Self-motivated individual with a strong sense of ownership, accountability, and teamwork.

📌 FCT Engineer (Bengaluru)
🏢 SignOff Semiconductors
📍 Bengaluru