Key Responsibilities:

Work onsite at Hyderabad as part of a distributed engineering team, collaborating closely with US-based counterparts on IP packaging deliverables

Apply foundational knowledge of chip design and design verification (DV) concepts to properly package, validate, and release IP for downstream consumption

Debug complex, multi-component systems including packaging pipelines, build flows, and design/verification environments to isolate root causes and drive fixes

Partner with design, DV, and build-system owners to understand IP requirements and ensure packaged deliverables meet quality and integration standards

Identify opportunities to apply AI tools to streamline packaging, debugging, or documentation workflows

Clearly document findings, issues, and packaging decisions, and communicate status and blockers proactively to stakeholders

Required Qualifications:

2-5 years of relevant qualified experience in semiconductor design, verification, IP packaging,



or related engineering domains

Working understanding of chip design fundamentals and design verification (DV) basics (e.g., RTL concepts, testbenches, simulation flows)

Demonstrated experience debugging complex systems (e.g., tracing failures across tools, scripts, or design/verification/packaging flows to root cause)

High analytical skills able to break down ambiguous or multi-layered problems methodically

Exceptional written and verbal communication skills able to clearly explain technical issues and status to both engineering peers and management across time zones

Willingness and ability to work onsite at the Hyderabad office.

Preferred Qualifications (Big Plus)

Understanding of hardware or software build systems (e.g., build orchestration, dependency management, CI/CD pipelines)

📌 Semiconductor Design Engineer (India)
🏢 Sunrisesys
📍 India