FPGA Design Engineer (VHDL)

Location: Mumbai, Maharashtra, India

Experience: 6-10 years

About the Company The hiring organization develops embedded electronic systems that combine FPGA-based processing, high-speed data acquisition, sensors, communication interfaces and hardware-software integration. Its engineering work spans product development from partially defined specifications and signal-mapping documentation through prototype validation and release. The organization values practical ownership, disciplined design governance and close collaboration across FPGA, Hardware, Embedded Software and Applications teams.

Engineers are expected to convert system requirements into reliable implementations, resolve issues at the correct architectural layer and maintain traceability from requirements through verification and validation. This project-based prospect supports ongoing development and refinement of FPGA-enabled systems, with scope that may evolve according to project priorities. The role offers direct influence over RTL architecture, laboratory bring-up, performance characterization and release readiness while working with Proto-1 hardware and established design documentation.

About the Role

Own the complete FPGA engineering lifecycle for embedded systems, from interpreting existing architecture and signal-mapping documentation through RTL implementation, verification, timing closure, hardware bring-up and system validation. Develop synthesizable VHDL in Vivado 2024.1 for Xilinx 7-series devices, including Spartan-7 and Artix-7 platforms. Build high-speed acquisition and processing paths for ADCs, DACs, DMA, AXI, AXI4-Stream, PCIe, Ethernet and serial peripherals. Establish reliable multi-clock, reset and CDC architectures, implement source-synchronous LVDS capture, and resolve timing and signal-integrity issues through sound RTL and architecture decisions.

Validate

Proto-1 hardware using simulation, Vivado Hardware Manager, ILA, VIO and laboratory instruments. Success means a reproducible, resource-efficient, timing-clean and system-validated FPGA release, supported by complete design, verification, bring-up and release documentation.

Key Responsibilities

- Own synthesizable VHDL RTL for high-speed ADC and DAC data paths, DMA, AXI and AXI4-Stream processing, protocol handling and peripheral interfaces, delivering reliable throughput within device resource limits.
- Implement and maintain multi-clock architectures using MMCMs and PLLs, with robust CDC, reset and FIFO structures that ensure deterministic transfers and prevent latent system failures.
- Develop source-synchronous LVDS capture using ISERDES, OSERDES, IDELAY and ODELAY, including bit and word alignment, framing, link training and ADC capture calibration.
- Author XDC constraints for clocks,



I/O timing, LVDS delays, false paths, multicycle paths and CDC max-delay paths, then drive implementation toward clean static timing.
- Verify modules and integrated subsystems through self-checking VHDL test benches, Vivado Simulator, regression testing and specification-based validation, documenting and resolving functional and interface defects.
- Bring up Proto-1 FPGA and DAQ hardware using Vivado Hardware Manager, ILA, VIO, oscilloscopes and logic analysers, isolating RTL, configuration, PCB, sensor and peripheral faults.
- Characterise synchronization skew, throughput, latency, dark-baseline stability, cross-card repeatability and data integrity, while supporting EMI/EMC pre-compliance investigations and corrective actions.
- Maintain scripted Vivado builds, MCS and QSPI programming flows, version-controlled release packages, register maps, interface definitions, design specifications, bring-up reports and milestone traceability.

Essential Skills & Technologies

- Strong hands-on VHDL and RTL design experience with AMD Xilinx 7-series devices, Vivado 2024.1, synthesis, place-and-route, resource optimisation and reproducible implementation flows.
- Proven expertise in FPGA timing closure, XDC constraints, CDC analysis, reset architecture, MMCM/PLL clocking, FIFOs, BRAM, DSP, setup and hold analysis.
- Practical experience with high-speed ADC or sensor acquisition, LVDS, ISERDES/OSERDES, IDELAY/ODELAY calibration, alignment, framing, signal integrity and hardware debugging.
- Working knowledge of AXI, AXI4-Stream, DMA, PCIe, Ethernet, SPI, I²C, UART, QSPI and RS-485 interface implementation, including packetisation and handshake semantics.
- Experience developing self-checking VHDL test benches, integration simulations, FPGA releases, QSPI configuration images and laboratory validation using ILA, VIO and test instruments.

Additional Plus

- Experience optimising designs for constrained devices such as XC7S25 while maintaining portable implementation across Spartan-7 and Artix-7 FPGA platforms.
- Exposure to image-sensor or detector interfaces, cross-channel synchronisation analysis, high-speed data integrity measurements and system latency characterisation.
- Familiarity with EMI/EMC pre-compliance debugging, clock-spectrum considerations, spread-spectrum configuration and firmware-side contributors to electromagnetic performance.

What You'll Bring





- You bring 6+ years of practical FPGA development experience and a strong foundation in Electronics through BE, BTech, ME or MTech education. You are comfortable owning RTL from architecture interpretation through implementation, verification, laboratory debugging and release, rather than limiting your contribution to isolated coding tasks.
- You can read existing FPGA specifications and signal maps, identify missing assumptions, and turn them into maintainable VHDL that meets functional, timing and resource requirements. You understand that clean timing requires architectural thinking, accurate constraints and disciplined CDC design, not inappropriate relaxation of requirements.
- You can use simulation and hardware evidence to separate RTL defects from configuration, PCB, sensor or peripheral problems. You communicate effectively with Hardware, Embedded Software and Applications teams while maintaining register maps, packet formats, interface contracts and design traceability.
- You work methodically under project milestones, document decisions and validation results, and remain adaptable when temporary project scope changes. Experience with Vivado 2024.1, Xilinx 7-series devices, high-speed LVDS or ADC acquisition, and hands-on Proto-1 bring-up will be particularly valuable.

Why Join Us

This role gives you end-to-end ownership of FPGA engineering across architecture, RTL, verification, timing closure, hardware bring-up and system validation. Your decisions directly determine whether embedded data-processing systems become reliable, measurable and release-ready.

You will work at the intersection of high-speed acquisition, FPGA processing, hardware integration and embedded software, solving problems that require both rigorous digital design and practical laboratory investigation.

The project-based structure provides a focused opportunity to deliver visible technical milestones, influence design governance and shape implementation decisions as system requirements and project priorities evolve.

What We Offer

- End-to-end technical ownership across FPGA design, verification, timing closure, hardware bring-up and system validation, with direct visibility into the business impact of each milestone.
- A cross-functional engineering environment where FPGA, Hardware, Embedded Software and Applications teams collaborate on integrated embedded-system outcomes.
- Project-based engagement with milestone-linked payment and scope flexibility, enabling the assignment to adapt to changing project requirements and delivery priorities.
- Hands-on access to prototype hardware, high-speed interfaces and professional FPGA debugging workflows, supporting practical problem-solving beyond simulation alone.

📌 FPGA Design Engineer (VHDL) (Maharashtra)
🏢 Metal Power Analytical
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