SoC DFT Engineer

Location: Bangalore

Notice Period: Immediate

Job Summary:

We are looking for a SoC DFT Engineer with hands-on experience in scan insertion, ATPG pattern generation, and scan rule and coverage debugging. The role involves gate-level simulations, working with JTAG/P1500 protocols, and scripting using Perl/Tcl.

Key Responsibilities:

- Perform scan insertion for SoC designs.
- Debug scan DRC violations and scan coverage issues.
- Generate ATPG patterns.
- Execute gate-level simulations, including zero-delay and timing-delay simulations.
- Work with JTAG and P1500 protocols.
- Develop and use Perl/Tcl scripts for DFT-related tasks.

Required Skills:

- 5+ years of experience in SoC DFT engineering.
- Hands-on experience in scan insertion, SCAN DRC, coverage debugging, and ATPG pattern generation.
- Experience with zero-delay and timing-delay gate-level simulations.
- Knowledge of JTAG and P1500 protocols.
- Proficiency in Perl/Tcl scripting.
- Knowledge of timing, formal verification, or physical design (PD) flows is an added advantage

📌 ACL Digital - SoC DFT Engineer (India)
🏢 ACL Digital
📍 India