17 Oct
|
Symphisys
|
Hyderabad
17 Oct
Symphisys
Hyderabad
Job highlights
Experience: 4+ Years .
Positive understanding of PCIe and CXL protocols is an added advantage
Location :Chennai
Experience: 4+ Years
Mandatory Skills
Robust Debug, UVM, System Verilog.
Understanding Specs and Standards and developing relevant test plans.
Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved.
Thorough understanding of Digital design concepts.
Thorough understanding dv methodologies and tools.
Valuable understanding of PCIe and CXL protocols is an added advantage.
Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite/CHI.
📌 Design Verification Engineer Systemverilog / Uvm / Pcie / Cxl / Axi Hyderabad
🏢 Symphisys
📍 Hyderabad