Job highlights
Implementation of a project with the full Cadence tools . Have worked on complex Hard macros with SerDes and / or critical in timing and area . Having experience in Flip-Chip SoC bump Ios) . Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file .
in PnR of a big SoC AMS with many partitions and not only blocks level implementation .
Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation
Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology)
Implementation of a project with the full Cadence tools
Have worked on complex Hard macros with SerDes and/or critical in timing and area
Having experience in Flip-Chip SoC bump Ios)
Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file