17 Oct
|
Semileaf
|
Hyderabad
17 Oct
Semileaf
Hyderabad
Job highlights
DRC,LVS DFM,Antenna,Density Fill Routines and other Tape-out sign-off experience is a must
Proficient in planning for and addressing electrical considerations throughout the design process (EM,IR,Noise,etc.)
Skills required
Physical verification at block-level& chip-level.
DRC, LVS DFM, Antenna, Density Fill Routines and other Tape-out sign-off experience is a must.
Tape-out experience of multiple complex chips at 14 nm or below is required.
Proficient in planning for and addressing electrical considerations throughout the design process (EM, IR, Noise, etc.).
Physical verification flow automation exposure will be an added advantage.
📌 Physical Verification Hyderabad
🏢 Semileaf
📍 Hyderabad