Job highlights
Experience in developing Micro architecture from specifications and take it upto RTL coding and synthesis
Should have worked on IP and SOC level Synthesis for multiple generations and be familiar with problems associated with different Process technologies
Experience in implementing ECOs
Sound knowledge of RTL design with Verilog/system Verilog and front-end design tools & flows.
Valuable experience in Synthesis & Timing Analysis required.
Experience in developing Micro architecture from specifications and take it upto RTL coding and synthesis.
Should have worked on IP and SOC level Synthesis for multiple generations and be familiar with problems associated with different Process technologies.
Should have experience working on Low power synthesis and understands UPF.
Experience in implementing ECOs.
IP development and coding using standard coding guide lines.
Must have solid knowledge of AMBA AHB/AXI protocol.
Working knowledge on code coverage, functional coverage, Lint, CDC Formality etc.

📌 Rtl Design Expert Pune (India)
🏢 Semileaf
📍 India