AMS Verification Engineer

*Experience:* 3–8 Years

*Location:* Hyderabad / Bangalore

*CTC:* 28 LPA

### JD / Required Skills

* Mixed-Signal Co-Simulation

* Full-chip or block-level simulations combining analog and digital engines

* *Cadence AMS Designer / Xcelium / Synopsys VCS*

* Behavioral modeling using *Verilog-AMS, Verilog, SystemVerilog RNM/wreal*

* SystemVerilog and UVM-AMS testbench development

* Debugging analog/digital interface issues, waveform anomalies, and simulation convergence failures

* Functional coverage closure

* Automation using *Python, Perl, or Tcl*

* Regression management and reporting

* Model vs. schematic verification

* Mixed-mode simulation with schematic/SPICE and behavioral models

* *SystemVerilog, UVM, Verilog/Verilog-AMS/SystemVerilog RNM*

* DLL, DCC,



ZQ Calibration, Bandgap, ADC, DAC, PLL, LDO

* *Cadence Virtuoso, Spectre, Xcelium*

* Robust hands-on mixed-signal/co-simulation verification experience

### Additional Requirements

* AMS, co-simulation, UVM – *6+ Years*

* Tools: *Spectre, Virtuoso, Xcelium*

* Circuit understanding – *4+ Years*

* Block-level (IP) simulation – *4+ Years*

* Pattern development – *2+ Years*

* Design validation – *4+ Years*

* Measurement, Analysis, Characterization – *3+ Years*

Pay: Up to ₹2,800,000.00 per year

Work Location: In person

📌 AMS Verification Engineer (Bengaluru)
🏢 Clock Edge Technologies Pvt Lt
📍 Bengaluru