Solid expertise in SoC performance architecture and pre-silicon performance analysis, including:
- Hands-on experience with simulation and hardware emulation platforms such as Palladium, Veloce, ZeBu, or equivalent
- Performance analysis using cycle-accurate, transaction-level, and emulation-based environments
- Waveform-based debug and signal-level performance analysis
- Latency, bandwidth, throughput, QoS, and utilization characterization
- Transaction-level tracing and protocol debug across CHI, AXI, PCIe, CXL, or equivalent system protocols
- Identification of system-level bottlenecks across compute, interconnect, memory, and IO subsystems
- Architectural tradeoff analysis across performance, power, area, latency, bandwidth, and implementation complexity