Job highlights

- Senior ASIC/ FPGA Design Verification Engineer Job Code: AL_FPGA_IND_01 Required skills: As a Design engineer should be able to develop design specs,HDL based RTL.Strong knowledge on Digital design concepts with RTL implementation (Verilog/ VHDL).Experience with FPGA/ ASIC tool flows for Logic Synthesis,STA and Frontend Design
- Good in concepts of code coverage and Functional coverage

Senior ASIC/ FPGA Design Verification Engineer Job Code: AL_FPGA_IND_01 Required skills: As a Design engineer should be able to develop design specs, HDL based RTL

Strong knowledge on Digital design concepts with RTL implementation (Verilog/ VHDL)

Experience with FPGA/ ASIC tool flows for Logic Synthesis, STA and Frontend Design.





Expertise in RTL top level integration and should have excellent debugging skills.

As a Verification engineer Working on full chip Verification and OVM/ UVM Methodology,

System Verilog is a must with 3+ years of work experience,

Worked on passing test cases, test benches, Building workplace.

Good knowledge of Functional coverage using HVL language features or assertions a plus.

Good in concepts of code coverage and Functional coverage.

Strong domain knowledge on PCI/ PCIe Verification / Ethernet MAC/ DDR/ PHY

Knowledge to develop required script to complete verification using Perl, Shell or Python preferable

📌 Senior ASIC/FPGA Design Verification Engineer (Bengaluru)
🏢 Atria Logic
📍 Bengaluru