- Good knowledge on AMBA protocols such as APB,AHB and AXI
- Experience with synthesis tools (e.g.,Synopsys Design Compiler)
- Experience with low-power design techniques
- . Additional Skills : . SoC Integration experience is an added advantage
- Knowledge and Experience wth Design IPS of PCIe Gen5,I2C,UCI and HBM,etc
Synopsys Design Compiler, SpyGlass , SpyGlass CDC, Cadence Genus, JasperGold or similar We are seeking a highly skilled RTL Design Engineers for various RTL Design positions, to join our dynamic team. RTL design Engineers with IP level, SoC Integration and with expertise in PCIe.
This is a consolidated RTL Design .
Roles and Responsibilities :
- Develop and implement RTL code for various IP blocks using Verilog/SystemVerilog.
- Experience with synthesis tools (e.g., Synopsys Design Compiler).
- Familiarity with linting tools (e.g., SpyGlass or similar).
- Strong understanding of CDC analysis and tools (e.g., SpyGlass CDC or similar).
- Excellent problem-solving and debugging skills.
- Strong communication and teamwork skills.
- Experience with low-power design techniques.
- Knowledge of scripting languages (e.g., Python, Tcl).
Additional Skills :
- SoC Integration experience is an added advantage.
- Strong understanding of PCIe protocol and its implementation.
- Knowledge and Experience wth Design IPS of PCIe Gen5, I2C, UCI and HBM, etc.
- Positive knowledge on AMBA protocols such as APB, AHB and AXI.