Job highlights

- Required Skills & Experience . 3 5 years
- bus protocols (AMBA preferred),resets,clocking,and power domains
- Preferred Qualifications
- Experience: 3 5 years
- of experience in
- . Hands-on experience with
- Experience with EDA tools for linting,CDC / RDC,and synthesis (Synopsys,Cadence,Siemens tools)
- Experience with

RTL Design & Verification Engineer Location: Bangalore, Karnataka, India

Experience: 3 5 years

Role Overview

We are looking for a highly skilled RTL Design & Verification Engineer with strong expertise in digital ASIC design, memory IP integration, and SoC-level development. The ideal candidate will drive micro architecture, deliver high quality RTL, and collaborate closely with cross functional teams to ensure first time right silicon.

Key Responsibilities RTL Design & Micro Architecture

1. Drive micro-architecture definition , review design specifications, and participate in architecture discussions.
2. Develop high-quality RTL in Verilog/SystemVerilog for complex digital blocks and subsystems.
3. Perform design partitioning , define clock/power domains, reset strategies, and interface specifications.

Memory IP & SoC Integration

1. Integrate various Memory IPs including SRAM, ROM

.

2. Work on SoC-level integration , interface definition, and system-level design convergence.
3. Debug and resolve issues related to memory controllers, address decoding, timing, and SoC integration.

RTL Quality & Signoff Metrics

1. Own RTL quality metrics including:
2. Lint
3.



CDC (Clock Domain Crossing)
4. RDC (Reset Domain Crossing)

5. Synthesis QoR
6. Timing closure readiness
7. Collaborate with PD, STA, DFT, and verification teams to achieve signoff-quality RTL.

Cross-Functional Collaboration

1. Work closely with architecture , verification , physical design , DFT , and firmware teams.
2. Provide hands-on guidance to junior engineers on RTL design and documentation best practices.

3. Participate in design reviews , code walkthroughs, and cross-functional checkpoints.

Required Skills & Experience

1. 3 5 years of experience in RTL design and/or verification for digital ASICs.

2. Strong expertise in Verilog/SystemVerilog , digital logic design, and micro-architecture.
3. Hands-on experience with Memory IP integration (SRAM, ROM, EEPROM, OTP/NVM).
4. Solid understanding of SoC architecture , bus protocols (AMBA preferred), resets, clocking, and power domains.

5. Experience with EDA tools for linting, CDC/RDC, and synthesis (Synopsys, Cadence, Siemens tools).
6. Ability to analyze synthesis reports, perform timing-driven fixes, and collaborate with STA teams.
7. Excellent problem-solving skills and ability to work in a quick-paced design environment.

Preferred Qualifications

1. Exposure to design verification using UVM or SystemVerilog TB.
2. Experience with low-power design (UPF), multi-power domains.

3. Knowledge of DFT concepts, scan insertion, and ATPG.
4. Familiarity with scripting languages like Python, Perl, or Tcl .

📌 RTL Design & Verification Engineer (Bengaluru)
🏢 Genisup India
📍 Bengaluru