- . Proficient in the physical verification process,including antenna checks,ERC,and DFM
- Demonstrated knowledge and experience in the complete physical design flow
- Experience of Clock Tree Synthesis (CTS)
- Experience in Static Timing Analysis (STA)
- Experience in Placement and Floor Planning
- . Hands-on experience in achieving DRC and LVS closure
- Demonstrated knowledge and experience in the complete physical design flow.
- Experience of Clock Tree Synthesis (CTS).
- Experience in Static Timing Analysis (STA).
- Experience in Placement and Floor Planning.
- Proficient in the physical verification process, including antenna checks, ERC, and DFM.
- Hands-on experience in achieving DRC and LVS closure.
- Extensive experience with CAD tools such as Synopsys ICC, FC, Cadence Tempus, Innovus Encounter or similar.
- Experience with advanced technology nodes including 3nm, 5nm, 7nm, and 10nm.
- Experience with scripting Languages (TCL, Perl and Python).
- Prior experience with tape-out at client sites is highly advantageous.
- Ability to interact and coordinate with cross functional teams such as Circuit Designers and RTL Engineers.
- Solid communication skills to facilitate collaboration and project success.