- 4-8 years of hands-on Design Verification experience, preferably at IP/Sub-System level.
- Strong proficiency in SystemVerilog and UVM.
- Strong understanding and hands-on verification experience with the PCI Express (PCIe) protocol.
- Positive knowledge of PCIe architectural concepts including:
Transaction Layer
Data Link Layer
TLPs
LTSSM / Link Training
Configuration Space
Flow Control
Error Handling & Recovery
- Hands-on experience with PCIe Gen3/Gen4, with Gen5 exposure desirable.
- Experience developing reusable UVM verification environments, sequences, monitors, checkers, scoreboards, and coverage models.
- Good knowledge of constrained-random verification, functional coverage, code coverage, and assertions.
- Experience with industry-standard simulation/debug tools such as VCS, Xcelium or QuestaSim.
- Strong ability to debug RTL, UVM testbench, simulation, regression, and protocol-related failures.