- 9-25 years experience with expertise in SV UVM testbench setup, DFT-DV verification, and knowledge of protocols like PCIe, USB, Ethernet
- Lead Cluster Project team, develop UVM sequences and tests, perform waveform debugging and verification tasks
Dear Candidate, Greetings from Mirafra Technologies!
We are looking for an experienced Lead Design Verification Engineer (HYBRID)to join our team, This position is lead a Cluster Project team in Hyderabad.
- Familiarity with SoCs and boot flow would be useful.
- • SV UVM based TB environment setup, usage of UVM VIPs.
- • Developing UVM sequences, tests, TB bring up and sanity regressions.
- • Familiarity with Software development flow including assembly and C is beneficial.
- • Knowledge of system-level architecture including buses like AXI/CHI/ACE5, bridges,
memory controllers such as DDR5/LPDDR5/DDR4/LPDDR4
- • Knowledge of one or more protocols; PCIe, USB, Ethernet
- • Sound knowledge on UPF and power domain crossing
- • Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi
- • Strong expertise in DFT-DV verification, like Scan clear / Mem transparent / JTAG / IJTAG / Memory repair, Scan dump, ATPG etc
Experience: 9 to 25 Years Notice Period: 0 to 60 Days
Employee referrals are highly appreciated!
Please note: Mirafra does not charge any fees for job applications, interviews, or hiring, nor have we authorised anyone to collect money on our behalf.