Key Responsibilities

DFT Implementation

- Develop and implement DFT architecture for complex SoCs and IPs.

- Perform Scan Insertion using

Cadence Modus DFT

.

- Define and implement:

- Full Scan

- Scan Compression

- Scan Chain Stitching

- Test Point Insertion

- Boundary Scan (JTAG)

- MBIST Integration

- LBIST (Preferred)

ATPG & Fault Coverage

- Generate ATPG patterns using Cadence Modus.

- Analyze and improve fault coverage.

- Debug pattern generation issues and coverage gaps.

- Perform diagnostics and failure analysis.

Synthesis & DFT Flow

- Execute synthesis using

Cadence Genus

.

- Work closely with RTL and Physical Design teams for DFT signoff.

- Support timing closure of DFT logic.

- Optimize DFT structures with minimal impact on PPA.

Verification & Validation

- Perform DFT verification at RTL and gate level.

- Validate scan chains and test modes.

- Run simulations for:

- Scan Shift

- Capture Mode

- ATPG Pattern Validation

- MBIST Verification

Silicon Bring-Up

- Support post-silicon validation and production testing.

- Analyze ATE test results and debug manufacturing failures.

- Collaborate with Product Engineering and Test Engineering teams.

📌 Design-for-Test (DFT) (Bengaluru)
🏢 Cyient
📍 Bengaluru