What You'll Own

- Define and implement MLIR dialects and lowering pipelines targeting our AI-accelerator/NPU platform.

- Lower ML graphs (e.g., from ONNX/PyTorch) into optimized kernels focusing on fusion, tiling and vectorization.

- Profile, benchmark and optimize compiler output to meet latency, throughput and power targets.

- Work with hardware architects and runtime/framework teams to co-design compiler features.

- Build a future‐ready, portable compiler stack that supports multiple hardware generations.

Minimum Qualifications

- 5+ years of experience in compiler engineering or high‐performance systems.

- Strong programming skills in C++ (modern standards), and scripting or tooling in Python.

- Hands-on experience with MLIR and/or LLVM (designing/extending dialects, lowering, optimization).

- Deep understanding of compiler internals: IRs, code scheduling, vectorization, loop transformations.

- Strong familiarity with AI/ML frameworks (e.g.,PyTorch, ONNX, TensorFlow).

- Excellent understanding of ML operations such as tensor operators, matmuls, quantization, dynamic shapes.

- Robust understanding of computer architecture and memory hierarchy.

- Bachelor’s (or higher) degree in Computer Science, Computer Engineering or equivalent.

Preferred Qualifications

- Prior experience targeting NPU/AI accelerator hardware.

- Contributions to open‐source compiler projects (MLIR, LLVM,Torch-MLIR, ONNX-MLIR).

- Familiarity with runtime systems, scheduling, resource sharing, memory movement engines and, interconnects.

- Previous leadership role driving compiler architecture, setting standards, mentoring teams and owning roadmap.

- Familiarity with software development tooling: Git, CI/CD, debuggers, profilers.

- Advanced degree (M.S./Ph.D.) preferred.

What Success Looks Like (First 6–9 Months)

- A production compiler IR/dialect is designed and integrated,



successfully lowering key ML workloads to the target NPU.

- Key operator kernels (matmul, convolution, etc) show measurable performance gains (reduced latency, increased throughput) on the hardware or simulator.

- The compiler pipeline handles multi‐die/chiplet topology correctly and efficiently schedules across devices.

- Runtime interfaces and resource scheduling between host and accelerator are functional and validated with real workloads.

- Telemetry/debug hooks and performance counters from compiled code are available and used for performance analysis by other teams.

- The architecture and roadmap for next-gen hardware are defined, and junior engineers are actively mentored within the compiler team.

Qualifications

- Strong skills in compiler design and implementation, including parsing, semantic analysis, and code generation.

- Proficiency in one or more systems programming languages such as C, C++, Rust, or Go.

- Experience with performance optimization, including instruction-level tuning, memory management, and runtime efficiency.

- Familiarity with intermediate representations (IR), abstract syntax trees (AST), and optimization frameworks (e.g., LLVM or similar).

- Knowledge of operating systems concepts, low-level APIs, and build systems (e.g., CMake, Bazel, or similar).

- Ability to write clean, maintainable code, perform thorough code reviews, and create clear technical documentation.

- Bachelor’s or Master’s degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

- Robust analytical and problem-solving skills, with the ability to debug complex compiler and runtime issues.

- Comfort working in a remote, cross-functional team, with effective written and verbal communication skills.

- Experience in tooling development, static analysis, or language design is a plus.

📌 Complier Engineer (Hyderabad)
🏢 Teksands.ai
📍 Hyderabad