- Bachelor's or Master's degree in Electrical/Electronics Engineering or related field
- 4+ years of experience in IC package/substrate layout design
- Expert-level proficiency in Cadence Allegro Package Designer (APD/APD XL), SiP Layout, and Constraint Manager
- Solid understanding of substrate stackups, material selection, HDI technologies, via structures, package assembly processes, and reliability considerations
- Working knowledge of Signal Integrity, Power Integrity, impedance control, differential routing, PDN design, return path optimization, and crosstalk management
- Hands-on experience with high-speed interfaces including SerDes, PAM4, PCIe, DDR/LPDDR, HBM, Ethernet, CXL, USB, UCIe, and other multi-gigabit interfaces