- Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Science, or a related field.
- 3-5 years of hands-on experience in ASIC Design Verification.
- Strong expertise in:
- SystemVerilog (SV)
- UVM Methodology
- Constrained Randomization and Coverage-Driven Verification
- SystemVerilog Assertion (SVA)
- Hands-on experience in:
- ASIC - Subsystem, or IP Verification
- Testbench development from scratch
- DUT integration and verification environment development
- Experience with industry-standard EDA tools from Cadence or Synopsys.
- Positive scripting skills using one or more of the following:
- Shell Scripting
- Makefile