Company Description Chiplogic Technologies is an IP and product engineering services company founded in 2018, specializing in Semiconductor, Systems, IoT, and AI/ML domains. The organization delivers high-quality, dependable engineering services, supporting customers from concept to silicon across a wide range of semiconductor design and system solutions. Chiplogic provides Offshore Development Centers (ODC) and full turnkey design services, including proofs of concept and complete IoT system implementations.

Its AI/ML offerings are built around the proprietary VISARD™ (Video Synthesis And Real-time Dynamics) framework, enabling advanced video and real-time dynamics solutions for global clients.

Role Description We are seeking an experienced and self-driven Senior RTL Design Engineer to join our chip design team. In this role, you will play a crucial part in architecting, designing, and integrating complex, high-performance Subsystem and SoC-level designs for cutting-edge AI and High-Performance Computing (HPC) applications. You will collaborate closely with architecture, design verification, physical design, and firmware teams to deliver robust, high-quality silicon.

Key Responsibilities

- RTL Architecture & • Design:

Micro-architect and implement complex RTL modules and subsystems using SystemVerilog / Verilog for high-performance SoCs.
- SoC & • Subsystem Integration:

Integrate IP cores, busses, memory systems, and custom logic at both the Subsystem and top SoC levels.
- Debugging & • Root-Cause Analysis:

Perform extensive debugging and complex issue investigation across design stages, leading root-cause analysis and resolution.
- Cross-Functional Collaboration:
- Work with Design Verification (DV) teams to define test plans, review coverage,



and debug complex simulation fails.
- Partner with Physical Design (PD) teams on synthesis, timing closure (STA), floorplanning, and Power/Performance/Area (PPA) optimization.
- Collaborate with Architecture and Firmware teams to ensure seamless hardware-software integration.
- Linting & • CDC/RDC:

Run and clean Lint, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) checks.
- Design Quality & • Process:

Drive design reviews, maintain clean documentation, and follow best-in-class ASIC design methodologies.

Key Requirements & • Qualifications

- Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Microelectronics, VLSI Design, or a related field.
- Experience: 6+ years of hands-on experience in RTL Design and SoC-level integration.
- Technical Skills:
- Strong proficiency in SystemVerilog and/or Verilog for RTL design.
- Deep experience in Subsystem-level and SoC-level design and integration.
- Expert-level debugging skills with a proven track record of root-cause investigation and resolution.
- Proficiency in standard SoC interconnects/protocols (e.g., AXI, AHB, APB, PCIe, CXL, or TileLink).
- Hands-on experience with industry-standard EDA tools for Synthesis, Linting, CDC, and Static Timing Analysis (STA).
- Domain Exposure: Exposure to AI/ML accelerators, HPC chip architectures, or high-speed memory systems is a strong advantage.

Preferred Qualifications

- Experience with low-power design techniques (UPF/CPF, clock gating, power domain management).
- Familiarity with DFT (Design for Test) concepts and post-silicon bring-up/validation.
- Solid scriptwriting skills (Python, Perl, Tcl, or Bash) for design automation.
- Immediate availability or ability to join at short notice.

📌 RTL Design Engineer (Bengaluru)
🏢 Chiplogic Technologies
📍 Bengaluru