Hiring: DFT Lead / Techno-Managerial Engineer

Location: Bangalore | Experience: 8–18 years

Role Overview

Lead end-to-end Design for Test (DFT) activities for complex SoC designs, combining hands-on technical ownership with team leadership and project delivery.

Key Responsibilities

- Define and implement DFT architecture, including scan insertion, compression, ATPG, MBIST and JTAG/boundary scan.
- Drive test coverage closure, pattern generation, simulation and debugging.
- Collaborate with RTL, verification, physical design and test teams to resolve DFT integration, timing and testability issues.
- Support silicon bring-up, ATE pattern debugging and diagnosis.
- Review technical deliverables, mentor engineers and drive quality across DFT milestones.
- For techno-managerial roles, manage resource planning, schedules, delivery risks and stakeholder communication.





Required Skills & Qualifications

- B.E./B.Tech/M.Tech in Electronics, Electrical Engineering or a related discipline.
- 8–18 years of relevant DFT experience, including technical leadership.
- Strong expertise in scan methodologies, ATPG, fault models, test coverage analysis and memory testing.
- Hands-on experience with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX or Cadence Modus.
- Proficiency in Verilog/SystemVerilog and scripting using Tcl, Python or Perl.
- Experience with multiple SoC tape-outs and solid debugging, problem-solving and communication skills.
- For techno-managerial positions, proven experience leading teams and owning project delivery.

📌 DFT Lead / Manager (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru