Role : AIML Engineer L1(Senior circuit verification)-MIC Location :Hyderabad ( WFO - 5 Days ) Experience Level :5 - 9 Years Budget : 10 - 16 LPA

Must have Skills : Python, SPICE/FastSPICE Simulation, Circuit Simulation &Verification;, DC Analysis & Transient Analysis, Analog/Mixed-Signal Circuit Verification, Memory Schematics & Building Block Schematics, Circuit Characterization & Timing Libraries, Verilog MOS Switch-Level Modeling, Gate-Level Simulation & Debugging, Latch-Based Design Verification, PVT Corner Analysis, Monte Carlo & Mismatch Simulation, EM, IR Drop, ESD & BTI Analysis

Job Summary

- Perform block-level SPICE/FastSPICE simulations for analog and mixed-signal circuits.
- Conduct pre-layout and post-layout simulations, including analysis of extracted netlists with parasitic R, C, L, and coupling capacitances.
- Execute PVT corner, Monte Carlo, and mismatch simulations to validate circuit functionality and yield.
- Perform reliability analyses including Electromigration (EM), IR Drop, ESD, and BTI/Aging checks.




- Develop and understand building block schematics and memory schematics.
- Run circuit simulations, including DC and transient analysis.
- Analyze and interpret circuit behavior from schematics.
- Work with circuit characterization, timing libraries, timing arcs, and related file formats.
- Perform Verilog MOS switch-level modeling and netlist simulations using zero-delay, unit-delay, and path-delay methodologies.
- Verify latch-based designs and their timing requirements.
- Debug gate-level simulation failures and identify root causes at the circuit level.
- Collaborate with layout engineers to optimize floorplanning and reduce parasitic effects.
- Work closely with design engineers to resolve circuit performance and functional issues.
- Develop automation scripts for simulation workflows, data extraction, and result formatting.

Pay: ₹1,000,000.00 - ₹1,600,000.00 per year

Work Location: In person

📌 Aiml Engineer(Senior Circuit Verification) - mic (Hyderabad)
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