Staff Engineer – STA & Synthesis

Location: Bengaluru

Experience: 7–12 Years

Role Overview

We are looking for a technically solid Staff Engineer with hands-on expertise in Static Timing Analysis (STA) and RTL-to-gate synthesis for complex ASIC/SoC designs. The role focuses on timing closure, synthesis optimization, constraint development, and PPA improvement across advanced technology nodes.

Key Responsibilities
Drive RTL synthesis, timing analysis, and optimization for complex IP and SoC designs.
Develop, validate, and maintain timing constraints using SDC, including clocks, generated clocks, exceptions, and I/O delays.
Perform setup/hold analysis, timing path analysis, and root-cause debugging across PVT corners and operating modes.
Optimize synthesis results for timing, power, and area (PPA).
Analyze and resolve timing violations involving logic depth, fanout, transition, capacitance, and interconnect effects.
Execute multi-mode, multi-corner (MMMC) STA and support timing closure across implementation stages.
Collaborate with RTL, Physical Design, DFT, and architecture teams to resolve timing and synthesis challenges.
Perform equivalence checks and ensure consistency between RTL and synthesized netlists.
Drive sign-off readiness through timing reports,



constraint validation, and systematic violation closure.

Required Technical Skills
7–12 years of hands-on experience in STA and RTL synthesis for ASIC/SoC designs.
Solid expertise in Synopsys PrimeTime and Design Compiler or equivalent industry-standard tools.
Proficiency in SDC constraints, timing exceptions, clock definitions, and constraint debugging.
Strong understanding of setup/hold timing, clock uncertainty, skew, latency, and signal integrity effects.
Experience with MMMC analysis, timing derates, OCV/AOCV/POCV, and PVT corner analysis.
Robust knowledge of synthesis optimization, timing-driven mapping, and PPA trade-offs.
Experience analyzing timing reports and driving root-cause resolution.
Proficiency in Tcl scripting and automation using Python or Perl.

Preferred Qualifications
Experience with advanced technology nodes and high-performance SoC designs.
Exposure to physical-aware synthesis, post-route timing correlation, and sign-off STA.
Understanding of low-power design techniques and DFT-related timing considerations.

Education: B.E./B.Tech/M.E./M.Tech in Electrical Engineering, Electronics, or a related discipline.

📌 Staff Engineer Sta & Synthesis Bengaluru
🏢 leadsoc technologies
📍 Bengaluru