Verification Architecture & Strategy
Architect and drive end-to-end verification strategies for complex NPU and RISC-V based SoCs.
Define verification plans, test strategies, coverage metrics, and closure methodologies.
Develop scalable and reusable verification settings using UVM.
Leverage Formal Verification techniques to accelerate verification closure.

NPU & AI Accelerator Verification
Verify AI/ML accelerator architectures including:
Neural Processing Units (NPU)
Tensor Processing Engines
Matrix Compute Units
MAC Arrays
Vector Processing Engines
AI Data Movement Architectures
Validate functionality, performance, and architecture compliance.

RISC-V Verification
Verify RISC-V processor subsystems and integration.
Validate:
Pipeline Functionality
Cache Subsystems
Interrupt Controllers
MMU and Memory Subsystems
Privileged Architecture
Multi-Core Operation
Develop processor verification scenarios and stress tests.

UVM-Based Verification




Develop and maintain:
UVM Agents
Drivers
Monitors
Scoreboards
Reference Models
Functional Coverage Models
Create constrained-random and directed test scenarios.
Drive verification closure using coverage-driven methodologies.

Formal Verification
Architect and execute Formal Verification solutions.
Perform:
Property Verification
Assertion-Based Verification (SVA)
Connectivity Verification
Deadlock Analysis
Security Checks
Protocol Compliance Verification
Formal Coverage Analysis
Integrate Formal methodologies with simulation-based verification.

SoC Verification
Verify complex SoC subsystems involving:
RISC-V CPUs
NPUs
NoC Fabric
Memory Controllers
DMA Engines
High-Speed Interfaces

Collaborate with RTL, Architecture, DFT, Firmware, and Software teams

📌 Design Verification Lead Bengaluru
🏢 Cyient
📍 Bengaluru