Preferred candidate profile
The candidate must have excellent written and spoken communications, sufficient to present program technical status & schedule progress to senior management.
Technical requirements:
Solid experience with the Cadence suite of EDA tools
Deep and broad expertise in functional AMS verification of RFICs including RF/Analog/Digital content
Develop and maintain verification plans, strategies and methodology
Perform functional, behavioral and regression verification
Collaborate with RF designers and chip leads for successful tapeout and release of products to guarantee first-pass success
Automate verification flows and reporting infrastructure
Solid debug and root-cause analysis skills
Circuit Analysis:
Understanding of analog blocks including low bit count data converters (ADC & DAC blocks), Bandgaps, Op-Amps, Bias blocks, Charge-pumps, Temp sensor, LDO, ESD, e-fuse and other supporting cells.
Knowledge of RF SOI technology including RF switch, tuning & RF LNA design.
Digital Design including SPI & MIPI interface design, Decoding logic, and straightforward state machines.
Semiconductor device and process knowledge including SOI, bulk CMOS, SiGe.