Job Description
Arm’s Physical IP Division develops Physical IP that is extensively used by SoC designers around the world to build sophisticated, high-performance chips on groundbreaking process nodes.
We are seeking a highly skilled and technically proficient engineer with experience in ASIC front-end design methodologies across IP and SoC design domains, to join the Design Enablement team within Solutions Engineering - Implementation organization. The role will focus on developing and deploying models for various types of Physical IP, including standard cells, embedded memories, and custom blocks.
Responsibilities
• Work alongside IP design teams to grasp the functionality and implementation of Physical IP. Coordinate with EDA vendors and SoC design teams to set modeling requirements and specifications.
• Develop models according to specifications, validate them in relevant EDA flows, and deploy and support the models for production use.
• Develop robust validation methodologies to ensure model correctness, quality, and compatibility with downstream design flows.
• Automate model development, validation, and release workflows using scripting and software engineering techniques, including the effective use of LLMs and AI-assisted development tools.
• Continuously improve model quality, performance, development efficiency, and turnaround time.
• Investigate modeling and flow issues and work together with internal groups and EDA vendors to identify and apply solutions.
Vital Skills and Experience:
• Solid grasp of ASIC/SoC build flows, particularly simulation, synthesis, Design-for-Test (DFT), ATPG, and logic equivalence checking using industry-standard EDA tools.
• Experience with Verilog and SystemVerilog modeling and verification.
• Good understanding of digital circuit fundamentals, logic composition, and gate-level netlist.
• Strong automation and scripting skills using languages such as Python, Tcl, shell scripting, or Perl.
• Robust analytical and debug
📌 Senior Engineer- Modelling (Noida)
🏢 ARM
📍 Noida