This role is for one of Weekday’s clients Min

Experience:
4+ years

Location:
Noida JobType: full time Independently own DFT for 2–3 hierarchical blocks: scan insertion, ATPG, pattern simulation and debug, and handoff of block patterns to the top level. Support DFT-mode timing closure and post-silicon debug.

Experience:
4 to 5 years. Must have taken at least 2 projects to tapeout with block-level DFT ownership. Desired

Skills:
1. Scan insertion, scan compression and chain stitching at block level, with scan DRC debug and fixing. ATPG for stuck-at and transition (at-speed) fault models; meets coverage targets and analyses low-coverage causes (untestable, ATPG-untestable and aborted faults). 2. Pattern simulation with zero-delay and SDF-annotated (timing) gate-level simulation using VCS or Xcelium; debugs simulation failures. 3.



MBIST insertion and verification for block memories; basic understanding of memory repair. 4. JTAG (IEEE 1149.1) and boundary scan; exposure to IJTAG (IEEE 1687) networks. 5. Writes DFT constraints for synthesis and STA in shift and capture modes, and supports DFT-mode timing closure. 6. Pattern retargeting from core to top level in a hierarchical DFT flow. 7. Generates patterns and delivers them to the ATE team; supports debug of failing patterns on silicon. 8. Hands-on with Tessent, TestMAX / DFT Compiler, or Modus. 9. Scripting in Tcl, Python or Perl. LBIST exposure is a plus. Must-have skillsscan insertion, ATPG, Gate-level simulation Good-to-have skillsscan compression, chain stitching, scan DRC debug

📌 Sr DFT Engineer (Noida)
🏢 Weekday AI
📍 Noida