Are you an experienced STA Engineer looking to work on challenging ASIC/VLSI designs? Join our team and contribute to timing closure and sign-off.

Key Responsibilities
• Perform block-level and full-chip Static Timing Analysis (STA).
• Debug setup/hold violations and drive timing closure.
• Develop and validate SDC timing constraints.
• Perform MMMC analysis and timing sign-off.
• Analyze timing reports, clock skew, crosstalk, and OCV.
• Collaborate with Physical Design, RTL, and Synthesis teams. Required Skills
• 3+ years of hands-on STA experience.
• Synopsys PrimeTime or equivalent STA tools.
• Robust knowledge of SDC, MMMC, and timing closure.
• Understanding of CTS, parasitic extraction, and timing ECOs.
• Working knowledge of Tcl and Linux/Unix.

Education:
BE/BTech or ME/MTech in ECE, Electrical Engineering, VLSI, or a related field. Interested candidates are encouraged to apply #Hiring #STAEngineer #VLSI #ASIC #Semiconductor #PrimeTime

📌 Static Timing Analysis (Hyderabad)
🏢 leadIC Design
📍 Hyderabad