ASIC DV Engineer, Networking

Responsibilities:
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Perform simulation-based testing, including functional, performance, and compliance testing Stay up-to-date with industry trends, standards, and best practices related to Networking Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry Mentor other engineers to drive and deliver high confidence verification for highly complex ASIC projects. Minimum

Qualifications:
Bachelors degree in Electronics & Communication, Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Track record of first-pass success in ASIC development cycles At least 8 years of relevant experience Hands-on experience in Verilog, SystemVerilog, UVM , C/C,



Python based verification Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in one or more of the following areas along with functional verification
- Ethernet, 400G Mac, RDMA, TSO, LRO, PSP,ROCE (RDMA over converged Ethernet), Congestion Control etc Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Experience in IP, Cluster and SoC level verification in both RTL and Gate Level Setup Proficiency in scripting languages such as Python, Perl, or TCL to build tools and flows for verification environments Experience using analytical skills to craft novel solutions to tackle industry-level complex designs Demonstrated experience with effective collaboration with cross functional teams Preferred

Qualifications:
Experience in development of UVM based verification environments from scratch Experience with development of fully automated flows and scripts for data exploration, analysis and performance verification Experience with IP or integration verification of high-speed interfaces like Ethernet, PCIe, DDR, HBM Experience with verification of ARM/RISC-V based sub-systems or SoCs Experience in one or more of the following areas along with functional verification
- SV Assertions, Formal, Emulation Experience with revision control systems like Mercurial(Hg), Git or SVN Experience with simulators and waveform debugging tools Experience working across and building relationships with cross-functional design, model and emulation teams

📌 Senior Engineer/Lead engineer (Bengaluru)
🏢 Proxelera
📍 Bengaluru