Job highlights

- The candidate should have strong experience with STA tools like Tempus / Primetime
- The candidate should have in-depth knowledge of timing constraints. . Job Responsibilities

- Excellent oral and written communications skills to work with teams across the globe. . Strong understanding of timing closure and power optimization techniques. . Must have positive understanding of Verilog

Microchip AES Design team looking for an experienced and motivated Backend Implementation Engineer to perform STA for larger SOCs. As a member of the Implementation team, you will be responsible for timing constraints (SDC) generation and timing closure for multiple blocks and top level. The candidate should have strong experience with STA tools like Tempus/Primetime. The candidate should have in-depth knowledge of timing constraints.

Job Responsibilities

- Perform STA timing closure for multi-million hierarchical complex designs.

- Lead and drive team members to complete Implementation activities.

- Complete timing closure for blocks and top level in advanced nodes.

- Develop constraints/SDC and perform pre and post-layout timing closure.

- Experience on UPF/CPF would be an added advantage.

- Optimize design performance through timing closure and power optimization.

- Develop and maintain design constraints and timing models.





- Analyze and debug timing issues.

- Analyze physical timing challenges and provide guidance for placement and CTS.

- Occasional travel needed.

- Use metric-driven techniques to help ensure first-pass working silicon.

- Communicate regularly with the implementation and project team to resolve issues, and communicate status to Project Management.

Job Qualifications

This position requires at least B.E/B.Tech/M.Tech in Electronics with 7+ years of STA experience in a fast-paced environment with following experience.

- Expertise in Implementation activities: Static Timing/Crosstalk Analysis and timing closure.

- Expertise with STA Tools (Primetime or Tempus).

- Strong programming knowledge in Perl, TCL, and/or Shell and Python scripting.

- Excellent oral and written communications skills to work with teams across the globe.

- Strong understanding of timing closure and power optimization techniques.

- Must have good understanding of Verilog.

Travel Time

0% - 25%

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Sr Engineer II - Backend Implementation (Hyderabad)
🏢 Microchip Technology
📍 Hyderabad