- . Must have experience in Cadence / Synopsys EDA Tools
- . Should be self-motivated and take initiatives to drive new methodologies
- . Should have robust written and verbal communication skills
- . Hands-on experience in STA of large blocks / Sub-systems or / and full chip . .
- The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
- The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power.
- Must have experience in Cadence/Synopsys EDA Tools.
- Undertake full-chip flat / block level database timing analysis and provide budgets or suggestions to Sub-system and Block owners for convergence.
- Hands-on experience in STA of large blocks/Sub-systems or/and full chip
- Expert user of industry standard tools fortiming signoff especially Synopsys PT.
- Expert in scripting languages (shell, perl, tcl) and Make flow.
- In-depth knowledge of 7nm/5nm/3nm technologies and associatedphysicaldesign challenges.
- Should be self-motivated and take initiatives to drive new methodologies.
- Should have strong written and verbal communication skills.