- Experience in DFT architecture, scan insertion, ATPG, MBIST, and IJTAG implementation for complex SoC designs
- Define and implement DFT architecture, perform scan insertion and compression, generate ATPG patterns, validate MBIST and IJTAG, debug GLS, and collaborate across teams for DFT signoff
Define and implement DFT architecture for complex SoC designs. Perform synthesis and scan insertion.
Implement and optimize scan compression techniques to improve test efficiency.
Develop and integrate Streamline Fabric/ SSN solutions.
Execute IJTAG (IEEE 1687) insertion and validation.
Implement and validate MBIST/SMS (Shared Memory System) architectures.
Perform memory repair and redundancy analysis where applicable.
Generate ATPG patterns and perform fault simulation for Stuck-at, Transition, and other fault models.
Debug and execute Gate-Level Simulations (GLS).
Perform Formality and Logical Equivalence Check (LEC) signoff.
Analyze test coverage and drive improvements in DFT quality metrics.
Collaborate with RTL, Verification, Physical Design, and Product Engineering teams to resolve DFT-related issues.
Drive DFT signoff and support silicon bring-up activities.