- 5-8 years in design verification with SystemVerilog and UVM expertise, PCIe Gen5/Gen6 hands-on experience
- Develop and execute verification testbenches, debug and close coverage, build UVM components from scratch
5 to 8 years of experience in design verification in a fast-paced development environment.
- Solid understanding of the complete verification lifecycle, including test planning, testbench development, execution, debug, and coverage closure.
- Strong hands-on experience in System Verilog and UVM.
- Good working knowledge of PCIe and AMBA protocols.
- Minimum 1 year of hands-on experience in PCIe Gen5 or Gen6 is mandatory.
- Proven expertise in developing UVM testbench environments and verification components such as drivers, monitors, scoreboards, and agents from scratch.
- Self-motivated and result-oriented, with strong debugging, analytical, and communication skills.