- Experience in RTL and Gate level Power aware simulations of scan and MBIST test vectors .
- In depth knowledge of DFT concepts,hands on experience in scan insertion,ATPG,coverage analysis,Transition delay test coverage analysis .
- In depth knowledge and hands on experience in LBIST insertion . .
- In depth knowledge of DFT concepts, hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis
- In depth knowledge and hands on experience in LBIST insertion
- Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations.
- Expertise in scripting languages such as perl, shell, phython etc.
- Experience in RTL and Gate level Power aware simulations of scan and MBIST test vectors
- Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (Tessent)