Job highlights

- Working experience in System Verilog,Vera,modelsim tools . Ability to work in an international team,dynamic environment . Ability to learn and adapt to new tools and methodologies
- Minimum of 8 -12 year experience in ASIC / DFT and various aspects simulation,Silicon validation .
- . In-depth knowledge and hands on experience in Silicon debug,yield optimization . .

:
- Be a member of the team that plays a significant role in ensuring the quality of next generation processors for Smart phones and Smart card through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include Interfacing with the design teams to ensure DFT design rules and guidelines are met.
- Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on-chip test compression techniques. MBIST verification and test pattern generation through Mentor tool.
- Work closely with design team on IDDQ constrains validation and pattern generation along with IVA analysis.
- Simulating and verifying the ATPG (SAF, TDF) and MBIST patterns on unit delay and min/max timing corners.
- Working with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE debug.
- Lead team of 2-3 engineers working bin DFT/ADFT pattern generation and validation
- Contribute to technical innovation,



development of innovative techniques in the area of test cost reduction, simulation time reduction and quality enhancement
- Responsible for supporting post Si debug effort, issue resolution
- Developing, enhancing and maintaining scripts as necessary.

Skills
- Minimum of 8 -12 year experience in ASIC/DFT and various aspects simulation, Silicon validation
- Detailed knowledge on DFT concepts, pattern simulation, Silicon debug
- In depth knowledge and hands on experience in ATPG, coverage analysis, Transition delay test coverage analysis.
- In-depth knowledge and hands on experience in Silicon debug, yield optimization
- Expertise in test mode timing constraints definition, Hands on experience with prime time is an added advantage
- Expertise in scripting languages such as perl, shell, etc. is an added advantage
- Knowledge/experience in post Si debug support
- Experience in simulating test vectors
- Working experience in System Verilog, Vera, modelsim tools
- Ability to work in an international team, dynamic environment
- Ability to learn and adapt to recent tools and methodologies.
- Ability to do multi-tasking work on several high priority designs in parallel.
- Past experience or ability to manage team

- Excellent problem solving skills
- Excellent communication and team work skills Experience with test tools such as Tetramax, Logic vision, Modelsim is highly desirable.

📌 DFT Lead (Hyderabad)
🏢 Ambit Semiconductors
📍 Hyderabad