Are you looking for a unique opportunity to be a part of something great Want to join a 17,000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust, empowerment, respect, diversity, and communication How about an prospect to own a piece of a multi-billion dollar (with a B!) People come to work at Microchip because we help design the technology that runs the world. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.

we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. The dsPIC Business Unit is seeking a Senior Technical Staff Engineer – Verification to join our team in Chandler, Arizona. You will work closely with cross-functional teams across the USA, India, and other global corporate teams to ensure high-quality verification results and timely project execution.





Develop assertions and coverage in System Verilog language, analyze coverage metrics, and drive coverage closure.

Debug RTL and testbench issues, perform root cause analysis, and collaborate with design and architecture teams to resolve defects.

Collaborate with architects, designers, and applications teams to verify IP and product requirements and deliver quality results on schedule.

Provide technical support and mentoring to verification engineers and drive projects to completion on schedule.

Bachelor's or master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.

Minimum 10+ years of experience in functional verification.

Strong expertise in SystemVerilog language, assertions, and UVM methodology.

Proven experience building IP-level and SoC-level verification environments using UVM and/or formal verification Testbenches.

Excellent understanding of digital design, RTL fundamentals, and ARM/RISC SoC architectures.

Highly motivated, detail-oriented, and committed to delivering quality results on time.

Experience driving methodology improvements and automation initiatives.

Travel Time

📌 Principal Engineer | Head Of Engineering (Bengaluru)
🏢 Microchip Technology
📍 Bengaluru