Design Verification Engineer (ASIC/SoC) | HCLTech We are hiring Design Verification Engineers with 5-10 years of experience in ASIC/SoC verification. ?
Location:
Bangalore / Chennai/Hyderabad/Vijayawada/Hubli/Cochin Skills Required ✅ UVM ✅ Formal Verification ✅ System Verilog / Verilog / VHDL ✅ ASIC/SoC Verification ✅ Testbench & Verification Setting Development ✅ Synopsys VCS, Cadence Xcelium/Incisive, ModelSim ✅ Python / Perl Scripting ✅ Debugging & Root Cause Analysis Preferred ✅ Experience in protocols -AMBA/AXI/DDR/ETHERNET/PCIE/UCIE is a plus. ⭐ Block-level and Subsystem-level verification experience ? Actively hiring If your experience matches, send your resume or DM me [email protected].