Physical Design Manager ASIC / SoC / VLSI 1. Position Details

- Location: Kalyan Nagar, Bangalore

- Work Mode: Hybrid

- Experience: 12 20 Years

- Domain: Semiconductor / ASIC / SoC / VLSI

- Role: Physical Design Manager

- People Management Experience: Minimum 3 Years (Mandatory)

2. Role Overview

We are looking for an experienced Physical Design Manager with 12 20 years of expertise in ASIC/SoC Physical Design and a minimum of 3 years of people management experience.

The role involves leading Physical Design teams, managing end-to-end chip implementation, and ensuring successful tapeouts across advanced semiconductor technology nodes.

The candidate should possess strong technical expertise in Physical Design, STA, Physical Verification, Power Integrity, and Signoff methodologies, along with proven team-building and project delivery experience.

3. Key Responsibilities

1. Lead and manage Physical Design engineering teams responsible for ASIC/SoC implementation and tapeout delivery.

2. Drive end-to-end Physical Design activities, including Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, Optimization, and Physical Signoff.

3. Manage full-chip and block-level Physical Design implementation across advanced technology nodes.

4. Provide technical leadership for Static Timing Analysis (STA), Timing Closure, and Signal Integrity (SI).

5. Oversee Power Integrity analysis, including Electromigration (EM), IR Drop, and Power Delivery Network (PDN) optimization.

6. Ensure Physical Verification and Signoff compliance, including DRC, LVS, and related checks.

7.



Lead low-power implementation methodologies using UPF/CPF and multi-voltage design techniques.

8. Drive PPA (Power, Performance, Area) optimization throughout the Physical Design flow.

9. Manage project planning, resource allocation, engineering schedules, technical risks, and tapeout milestones.

10. Build, mentor, and develop Physical Design teams through technical reviews, performance management, and capability development.

11. Collaborate with RTL Design, DFT, STA, Verification, CAD/EDA, and SoC Integration teams to resolve implementation challenges.

12. Establish Physical Design methodologies, review design quality, and ensure successful silicon tapeout execution.

4. Required Qualifications
- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline.

- 12 20 years of skilled experience in ASIC/SoC Physical Design.

- Minimum 3 years of direct people management experience (Mandatory).

- Proven experience in leading and building Physical Design engineering teams.

- Strong hands-on experience in advanced technology node implementation.

- Demonstrated experience in full-chip Physical Design and successful tapeouts.

- Strong understanding of Physical Design methodologies, timing closure, power integrity,



and physical signoff.

- Experience using Synopsys and/or Cadence EDA tool suites.

- Ability to manage multiple technical deliverables, engineering resources, and project schedules.

5. Technical Skills

A. ASIC / SoC Physical Design

- End-to-End Physical Design (RTL-to-GDSII)

- Full-Chip and Block-Level Implementation

- Floorplanning, Placement, CTS, Routing

- Physical Optimization and Timing Closure

- Advanced Technology Node Implementation

B. Timing and Signal Integrity

- Static Timing Analysis (STA)

- Setup and Hold Timing Closure

- Signal Integrity (SI) Analysis

- Crosstalk Analysis and Optimization

- Multi-Mode Multi-Corner (MMMC) Analysis

C. Power Integrity and Low-Power Design

- Electromigration (EM) Analysis

- IR Drop Analysis

- Power Delivery Network (PDN)

- UPF / CPF

- Low-Power Physical Design Methodologies

D. Physical Verification and Signoff

- Design Rule Checking (DRC)

- Layout Versus Schematic (LVS)

- Physical Signoff Methodologies

- Timing Signoff

- EM/IR Signoff

- Tapeout Readiness and Signoff Closure

E. EDA Tools

- Synopsys IC Compiler II (ICC2) / Fusion Compiler

- Cadence Innovus

- Synopsys PrimeTime

- Cadence Tempus

- Synopsys StarRC / Cadence Quantus

- Industry-standard Physical Verification and Power Integrity tools

F. Technical and People Leadership

- Physical Design Team Management

- Engineering Team Building and Mentoring

- Resource Planning and Project Execution

- Technical Reviews and Design Quality

- Cross-Functional Engineering Coordination

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📌 Physical Design Manager – ASIC / SoC / VLSI (Bengaluru)
🏢 Best NanoTech
📍 Bengaluru