Hiring: Memory Layout Engineer | 5+ Years Experience

Location:
Bangalore NP: Immediate to 60Days We are looking for experienced Memory Layout Engineers to join our team and work on advanced technology nodes. Key Requirements ✅ 5+ years of experience in Memory Layout Design ✅ Bachelor's degree in Electrical/Electronics Engineering or equivalent ✅ Strong experience in SRAM, ROM, RF, DRAM, or Flash Memory Layout Design ✅ Expertise in Memory Compiler/Custom Memory Layouts ✅ Hands-on experience with Cadence VLE/VXL, PVS, Assura, and Calibre DRC/LVS/ERC/Antenna ✅ Experience in advanced technology nodes such as TSMC 2nm/3nm and Samsung Foundry 2nm/3nm preferred ✅ Strong knowledge of LVS/DRC debugging, EM, ESD, Latch-up, IR-drop, Crosstalk, Shielding, and Critical Signal Routing ✅ Experience in designing Bitcell Arrays, Wordline Decoders, Sense Amplifiers, MUX, Control Blocks,



and Memory Periphery Circuits ✅ Multiple tape-out experience is an added advantage Responsibilities
• Design and develop memory layout blocks from leaf-cell to top-level integration
• Perform layout verification including LVS, DRC, Antenna, EM/IR checks, and quality reviews
• Collaborate with cross-functional and global engineering teams
• Drive high-quality layout implementation while meeting project milestones
• Resolve technical challenges and support successful tape-outs

What We Offer
• Opportunity to work on cutting-edge memory technologies and advanced nodes
• Collaborative and creative work environment
• Onsite opportunities available for candidates with 5+ years of relevant experience

📌 Memory Layout Engineer (Bengaluru)
🏢 Capgemini Engineering
📍 Bengaluru