Job Title: SystemC/TLM SoC Modelling EngineerLocation: Customer site
- Bangalore/Pune Years of

Experience:
10
- 12 Years Job Summary: We are seeking a highly skilled SystemC/TLM SoC Modelling Engineer with 3-5 years of hands-on experience in developing high-level virtual platforms and transaction-level models for complex System-on-Chip (SoC) architectures. The ideal candidate must possess robust proficiency in C++ and be adept at collaborating with cross-functional teams to ensure model accuracy and performance.

Key Responsibilities
• Develop, integrate, and validate SystemC/TLM 2.0 models for SoC components including CPUs, interconnects, peripherals, and memory subsystems.
• Create functional, performance, and loosely-timed (LT) / approximately-timed (AT) models for architecture exploration, hardware-software co-verification, and early software development.
• Collaborate with architecture, design, and verification teams to ensure model accuracy and performance.




• Debug and optimize simulation speed versus timing fidelity trade-offs. Mandatory

Skills:
• Strong proficiency in C++ (C++11 and modern standards).
• Expertise in SystemC/TLM-2.0 for modelling.
• Solid understanding of SoC architecture including processors, caches, coherency protocols, interconnects, and memory ordering.
• Experience with virtual platforms, performance modelling, and hardware-software co-simulation. Preferred

Skills:
• Exposure to tools like Synopsys Virtualizer, Cadence, or open-source SystemC environments.
• Familiarity with Python scripting, Git, and agile development methodologies.

Qualifications:
• Bachelor?s or Master?s degree in Electronics, Computer Engineering, or a related field. If you are passionate about SoC modelling and possess the required skills, we encourage you to apply and join our dynamic team.

📌 SENIOR TECHNICAL LEAD (Bengaluru)
🏢 Happiest Minds Technologies
📍 Bengaluru